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Niveau intermédiaire

This course is aimed at students with prior programming experience and a desire to understand computation approaches to problem solving.

Approx. 12 heures pour terminer

Recommandé : 4-10 hours/week...

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Sous-titres : Anglais

Compétences que vous acquerrez

Programming PrinciplesComputer ArchitectureProgramming Language Concepts

100 % en ligne

Commencez dès maintenant et apprenez aux horaires qui vous conviennent.

Dates limites flexibles

Réinitialisez les dates limites selon votre disponibilité.

Niveau intermédiaire

This course is aimed at students with prior programming experience and a desire to understand computation approaches to problem solving.

Approx. 12 heures pour terminer

Recommandé : 4-10 hours/week...

Anglais

Sous-titres : Anglais

Programme du cours : ce que vous apprendrez dans ce cours

Semaine
1
2 heures pour terminer

Familizarize youself with FPGA technologies

From the mid-1980s, reconfigurable computing has become a popular field due to the FPGA technology progress. An FPGA is a semiconductor device containing programmable logic components and programmable interconnects but no instruction fetch at run time, that is, FPGAs do not have a program counter. In most FPGAs, the logic components can be programmed to duplicate the functionality of basic logic gates or functional Intellectual Properties (IPs). FPGAs also include memory elements composed of simple flip-flops or more complex blocks of memories. Hence, FPGA has made possible the dynamic execution and configuration of both hardware and software on a single chip. This module provides a detailed description of FPGA technologies starting from a general description down to the discussion on the low-level configuration details of these devices, to the bitstream composition and the description of the configuration registers.

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9 vidéos (Total 57 min), 2 quiz
9 vidéos
FPGA-based systems and reconfiguration4 min
Programmable System-on-Multiple Chips7 min
Programmable System-on-Chips4 min
FPGAs main building blocks7 min
How to program an FPGA: bitstream and configuration5 min
How to program an FPGA: system description and physical design7 min
CAD Tools for FPGA-based systems design6 min
An introuction to the SDx development environment9 min
2 exercices pour s'entraîner
QUIZ 140 min
QUIZ 230 min
Semaine
2
3 heures pour terminer

A bird's eye view on SDAccel

The Xilinx SDAccel Development Environment let the user express kernels in OpenCL C, C++ and RTL (as an example we can think of, SystemVerilog, Verilog or VHDL) to run on Xilinx programmable platforms. The programmable platform is composed of (1) the SDAccel Xilinx Open Code Compiler (XOCC), (2) a Device Support Archive (DSA) which describes the hardware platform, (3) a software platform, (4) an accelerator board, and5. last but not least, the SDAccel OpenCL runtime. Within this module, after an introduction to OpenCL, we are going to see how this language has been sued in SDAccel and the main "components" of this toolchain.

...
7 vidéos (Total 37 min), 1 lecture, 1 quiz
7 vidéos
An introduction to SDAccel and the OpenCL-based flow5 min
OpenCL computational model: global and local sizes4 min
Not only OpenCL! The Rationale behind the RTL and C flows5 min
SDAccel memory model5 min
SDAccel "emulations"5 min
SDAccel runtime4 min
1 lectures
SDAccel Environment Programmers Guide2 h
1 exercices pour s'entraîner
QUIZ 330 min
Semaine
3
3 heures pour terminer

On how to optmize your system

Within this module, Before getting into the optimisation, we will first understand how an FPGA is working, also from a computational point of view. Although the traditional FPGA design flow is more similar to a regular IC than a processor, an FPGA provides significant cost advantages in comparison to an IC development effort and offers the same level of performance in most cases. Another advantage of the FPGA when compared to the IC is its ability to be dynamically reconfigured. This process, which is the same as loading a program in a processor, can affect part or all of the resources available in the FPGA fabric. When compared with processor architectures, the structures that comprise the FPGA fabric enable a high degree of parallelism in application execution. The custom processing architecture generated by SDAccel for an OpenCL kernel presents a different execution paradigm. This must be taken into account when deciding to port an application from a processor to an FPGA. To better understand such a scenario we will briefly compare a processor sequential execution with the intrinsic parallel nature of an FPGA implementation. Furthermore, within this module we are going to familiarise ourselves with the application optimisation flow.The Xilinx SDAccel Environment is a complete Software Development Environment, for creating, compiling, and optimising OpenCL applications with the objective of being accelerated on Xilinx FPGAs. From a designer perspective we can organise the flow for optimising an application in the SDAccel Environment as a three phases flow. Those three phases are: (1) baselining functionalities and performance, (2) optimising data movement and (3) optimising kernel computation

...
5 vidéos (Total 37 min), 1 lecture, 1 quiz
5 vidéos
FPGA Parallelism vs Processor Architecture 1/27 min
FPGA Parallelism vs Processor Architecture 2/28 min
Scheduling, Pipelining, and Dataflow8 min
Application Optimization Flow6 min
1 lectures
SDAccel Environment Profiling and Optimisation Guide1h 30min
1 exercices pour s'entraîner
QUIZ 430 min
5 heures pour terminer

Optimize your system via SDAccel

In this module we will provide a bird's eye view on the available SDAccel optimisations. The presented optimisations are not the only available ones, but they are more a list of recommendations to optimise the performance of an OpenCL application that have to be used as a starting point for ideas to consider or investigate further. Within this context we will organise these “recommendations” in three sets of optimisations: (1) arithmetic optimisations, (2) data-related optimisations, and finally (3) memory-related optimisations.

...
6 vidéos (Total 34 min), 2 lectures, 1 quiz
6 vidéos
Interface optimizations: Overall context and an overview of a typical target architecture6 min
Interface optimizations: a first example5 min
Burst data transfer3 min
Using full AXI data width4 min
Using multiple memory banks3 min
2 lectures
SDAccel Environment Profiling and Optimisation Guide2 h
Sources Codes1h 30min
1 exercices pour s'entraîner
QUIZ 530 min
Semaine
4
4 heures pour terminer

Other optimizations

After an overall description of possibile optimisations, within this module we will focus on four specific optimisations (1) loop unrolling, (2) loop pipelining, (3) array partitioning and (4) the host optimisations. First, we will describe loop unrolling which means to unroll the loop iterations so that, the number of iterations of the loop reduces, and the loop body performs extra computation. This technique allows to expose additional instruction level parallelism that Vivado HLS can exploit to implement the final hardware design. After that we will present the loop pipelining optimisation, where we will move from a sequential execution of the loop iterations to a pipelined execution in which the loop iterations are overlapped in time. After that we will present the array partitioning optimisation which allows to optimise the usage of BRAM resources in order to improve the performance of the kernel. Finally, at the end of this module we are going to discuss optimisations related to the host system that is responsible for transferring the data to and from the FPGA board, as well as to send the command to start the execution of a kernel.

...
6 vidéos (Total 43 min), 2 lectures, 1 quiz
6 vidéos
Kernel optimization: loop unrolling 2/26 min
Kernel optimization: loop pipelining9 min
Kernel optimization: array partitioning 1/28 min
Kernel optimization: array partitioning 2/27 min
Host optimizations5 min
2 lectures
SDAccel Environment Profiling and Optimisation Guide1h 30min
Source Codes1h 30min
1 exercices pour s'entraîner
QUIZ 630 min
3 heures pour terminer

An introduction to FPGA-augmented cloud infrastructures

...
3 vidéos (Total 14 min), 1 lecture, 1 quiz
3 vidéos
An introduction to SDAccel and the AWS EC2 F1 instances8 min
Closing remarks and future directions1 min
1 lectures
A Scalable FPGA Design for Cloud N-Body Simulation2 h
1 exercices pour s'entraîner
QUIZ 720 min

Enseignants

Avatar

Marco Domenico Santambrogio

Associate Professor
DEIB - Dept. of Electronics, Information and Bioengineering

À propos de Politecnico di Milano

Politecnico di Milano is a scientific-technological University, which trains engineers, architects and industrial designers. From 2014 Politecnico di Milano started the release of several MOOCs, developed by the service for digital learning METID (Methods and Innovative Technologies for Learning), giving everybody the chance to enhance personal skills....

Foire Aux Questions

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