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6 heures pour terminer

A Bird's Eye View on Adaptive Computing Systems

Nowadays the complexity of computing systems is skyrocketing. Programmers have to deal with extremely powerful computing systems that take time and considerable skills to be instructed to perform at their best. It is clear that it is not feasible to rely on human intervention to tune a system: conditions change frequently, rapidly, and unpredictably. It would be desirable to have the system automatically adapt to the mutating environment. This module analyzes the stated problem, embraces a radically new approach, and it introduces how software and hardware systems ca ben adjusted during execution. By doing this, we are going to introduce the Field Programmable Gate Arrays (FPGA) technologies and how they can be (re)configured.

7 vidéos (Total 29 min), 5 lectures, 5 quiz
7 vidéos
Reconfiguration in Everyday Life2 min
The Needs for Adaptation: an overview4 min
FPGA and reconfiguration: a 1st definition5 min
Runtime management2 min
Programmable System-on-Chip4 min
Programmable System-on-Multiple Chip6 min
5 lectures
Self-Aware Adaptation in FPGA-based Systems [suggested readings]30 min
Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores [suggested readings]1 h
Reconfigurable computing: a survey of systems and software [suggested readings]2 h
ReconOS: An Operating System Approach for Reconfigurable Computing [suggested readings]30 min
R3TOS-Based Autonomous Fault-Tolerant Systems [suggested readings]30 min
5 exercices pour s'entraîner
Reconfigurations15 min
History of Reconfiguration8 min
FPGA and reconfiguration6 min
Programmable SoC Vs SoMCs7 min
Runtime management4 min
5 heures pour terminer

An introduction to Reconfigurable Computing

Traditionally, computing was classified into General-Purpose Computing performed by a General-Purpose Processor (GPP) and Application-Specific Computing performed by an Application-Specific Integrated Circuit (ASIC). As a trade-off between the two extreme characteristics of GPP and ASIC, reconfigurable computing has combined the advantages of both. On one hand reconfigurable computing can have better performance with respect to a software implementation but paying this in terms of time to implement. On the other hand a reconfigurable device can be used to design a system without requiring the same design time and complexity compared to a full custom solution but being beaten in terms of performance. The main advantage of a reconfigurable system is its high flexibility, while its main disadvantage is the lack of a standard computing model. In this module we are presenting a first definition of reconfigurable computing, describing the rationale behind it and introducing how this field has been influenced by the introduction of the FPGAs.

5 vidéos (Total 27 min), 4 lectures, 2 quiz
5 vidéos
Reconfigurable Computing: HW vs SW3 min
On how to improve the Reconfigurable computing performance via CAD improvements3 min
FPGA-Based Reconfigurable Computing3 min
System design space exploration and rationale behind partial reconfiguration15 min
4 lectures
A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization [suggested readings]45 min
A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture [suggested readings]1 h
Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs [suggested readings]1 h
A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms [suggested readings]1h 30min
2 exercices pour s'entraîner
Reconfigurable Computing Module10 min
Performance4 min
4 heures pour terminer

Reconfigurable Computing and FPGAs

From the mid-1980s, reconfigurable computing has become a popular field due to the FPGA technology progress. An FPGA is a semiconductor device containing programmable logic components and programmable interconnects but no instruction fetch at run time, that is, FPGAs do not have a program counter. In most FPGAs, the logic components can be programmed to duplicate the functionality of basic logic gates or functional Intellectual Properties (IPs). FPGAs also include memory elements composed of simple flip-flops or more complex blocks of memories. Hence, FPGA has made possible the dynamic execution and configuration of both hardware and software on a single chip. This module provides a detailed description of FPGA technologies starting from a general description down to the discussion on the low-level configuration details of these devices, to the bitstream composition and the description of the configuration registers.

8 vidéos (Total 36 min), 3 lectures, 2 quiz
8 vidéos
FPGA Basic Block: CLBs and IOBs6 min
FPGA Basic Block: Interconnections5 min
FPGA Configuration: an overview2 min
More Details on How To Configure and FPGA: the bitstream files4 min
Bitstream Composition4 min
Configuration Registers6 min
How to handle the complexity of an FPGA-based system4 min
3 lectures
Note on the "Resources"1 min
Physical design for FPGAs [suggested readings]1h 30min
Multi-Million Gate FPGA Physical Design Challenges [suggested readings]1h 30min
2 exercices pour s'entraîner
Getting familiar with FPGAs34 min
FPGA configuration and Bitstream10 min
1 heure pour terminer

Examples on how to configure an FPGA

FPGA design tools must provide a design environment based on digital design concepts and components (gates, flip-flops, MUXs, etc.). They must hide the complexities of placement, routing and bitstream generation from the user. This module is not going through these steps in details, an entire course will be needed just for this, but it is important at least to have an idea of what it is happening behind the scene to better understand the complexity of the processes carried out by the tools you are going to use. Within this context, this module guides you through a simple example, which is abstracting the complexity of the underlying FPGA, starting from the description of the circuit you may be willing to implement to the bitstream used to configure the FPGA.

6 vidéos (Total 42 min), 2 quiz
6 vidéos
From the LUT to the CLB configuration example8 min
A simplified FPGA and its configuration settings4 min
An Example on how to implement a circuit on a simplified FPGA8 min
An Example on how to implement a circuit on a simplified FPGA: bitstram generation phase - CLBs5 min
An Example on how to implement a circuit on a simplified FPGA: bitstram generation phase - SBs and routing4 min
2 exercices pour s'entraîner
LUT and CLB4 min
Physical design4 min
5 heures pour terminer

An Introduction to Reconfigurations

Before continuing in this terrific journey in the reconfigurable computing area, it can be useful to define a common language. Obviously, some of these terms have been already used but it is now time to better understand them and to make some order before continuing with more advanced concepts. Furthermore, as we know, FPGA configuration capabilities allow a great flexibility in hardware design and, as a consequence, they make it possible to create a vast number of different reconfigurable systems. These can vary from systems composed of custom boards with FPGAs, often connected to a standard PC or workstation, to standalone systems including reconfigurable logic and General Purpose Processors, to System-on-Chip's, completely implemented within a single FPGA mounted on a board, with only few physical components for I/O interfacing. There are different models of reconfiguration, and a scheme to classify them is presented in this module. We can consider this module as a transitional/turning point module. We have been exposed to some terminology and concepts and we are now ready to move forward. To do this, we need to combine all the pieces of the puzzles together and to invest a bit at looking at the overall picture, and this is exactly what this module has been designed for.

5 vidéos (Total 35 min), 2 lectures, 2 quiz
5 vidéos
The 5 W's6 min
Reconfigurable Computing as an Exstension of HW/SW Codesing5 min
A Classification of SoC Reconfigurations8 min
A Classification of SoMC Reconfigurations9 min
2 lectures
Design methodology for partial dynamic reconfiguration: a new degree of freedom in the HW/SW codesign [suggested readings]1 h
Performance of partial reconfiguration in FPGA systems: A survey and a cost model [suggested readings]3 h
2 exercices pour s'entraîner
Functionalities and their implementations4 min
Module Review10 min
5 heures pour terminer

Towards Partial Dynamic Reconfiguration and Complex FPGA-based systems

The reconfiguration capabilities of FPGAs give the designers extended flexibility in terms of hardware maintainability. FPGAs can change the hardware functionalities mapped on them by taking the application offline, downloading a new configuration on the FPGA (and possibly new software for the processor, if any) and rebooting the system. Reconfiguration in this case is a process independent of the execution of the application. A different approach is the one that considers reconfiguration of the FPGA as part of the application itself, giving it the capability of adapting the hardware configured on the chip resources according to the needs of a particular situation during the execution time. In this case we are referring to this reconfiguration as dynamic reconfiguration and the reconfiguration process is seen as part of the application execution, and not as a stage prior to it. This module illustrates a particular technique, which is extending the previous two, that has been viable for most recent FPGA devices, Partial Dynamic Reconfiguration. To fully understand what this technique is, the concepts of reconfigurable computing, static and dynamic reconfiguration, and the taxonomy of dynamic reconfiguration itself must be analyzed. In this way partial dynamic reconfiguration can be correctly placed in the set of system development techniques that it is possible to implement on a modern FPGA chip.

8 vidéos (Total 40 min), 4 lectures, 2 quiz
8 vidéos
How to use FPGA Reconfiguration to face area issues5 min
How to deal with the Reconfiguration runtime overhead3 min
Recurring modules to reuse them to reduce the Reconfiguration time3 min
Partial Reconfiguration to reduce the Reconfiguration runtime overhead5 min
Runtime management to explore alternative implementations5 min
Bitstreams relocation6 min
Bitstreams relocation and virtual homogeneity3 min
4 lectures
Operating system runtime management of partially dynamically reconfigurable embedded systems [suggested readings]1 h
Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture [suggested readings]1 h
A runtime relocation based workflow for self dynamic reconfigurable systems design [suggested readings]1 h
Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux [suggested readings]1h 30min
2 exercices pour s'entraîner
Reconfigurable System6 min
Partial reconfiguration6 min
8 heures pour terminer

Design Flows

After presenting different solutions proposed to design and implement dynamic reconfigurable systems, this module will describe a general and complete design methodology that can be followed as a guideline for designing reconfigurable computing systems. To design and implement a reconfigurable computing system, designers need Computer-Aided Design (CAD) tools for system design and implementation, such as a design analysis tool for architecture design, a synthesis tool for hardware construction, a simulator for hardware behavior simulation, and a placement and routing tool for circuit layout. We may build these tools ourselves or we can also use commercial tools and platforms for reconfigurable system design. The first choice implies a considerable investment in terms of both time and effort to build a specific and optimized solution for the given problem, while the second one allows the re-use of knowledge, cores, and software to reach a good solution to the same problem more rapidly. This module is guiding the students through an historical view on how CAD frameworks evolved through the years. This is done to show how fast the technology is evolving and the rationale behind the choice made to improve the users experience when working with an FPGA-based system. Not only commercial tools are described, but also the personal journey done by the course instructor and his research team, starting from his early days as a PhD up to the research challenges they are nowadays working on.

9 vidéos (Total 54 min), 7 lectures, 3 quiz
9 vidéos
Partial Reconfiguration Design Flows4 min
Xilinx Difference Based Partial Reconfiguration5 min
Xilinx Module Based Partial Reconfiguration5 min
Xilinx Partial Reconfiguration (PR) Flow5 min
Moudle Based vs Partial Reconfiguration Design Flows17 min
Rationale behind DRESD and the work done by the Politecnico di Milano3 min
From DRESD to CHANGE and ASAP, two new research initiatives from the Politecnico di Milano4 min
CAOS: from embedded to heterogeneous distributed FPGA-based computing systems3 min
7 lectures
Vivado Design Suite Tutorial, Partial Reconfiguration, UG947 (v2016.1) April 6, 2016 [suggested readings - handbook - PDF]1h 30min
Vivado Design Suite User Guide, Partial Reconfiguration, UG909 (v2016.1) April 6, 2016 [suggested readings - handbook - PDF]3 h
Dynamic Reconfigurability in Embedded System Design [suggested readings]30 min
A design methodology for dynamic reconfiguration: the Caronte architecture [suggested readings]30 min
Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation [suggested readings]45 min
Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project [suggested readings]30 min
The Role of CAD Frameworks in Heterogeneous FPGA-Based Cloud Systems [suggested readings]30 min
3 exercices pour s'entraîner
Abstractions2 min
Politecnico di Milano Partial Reconfiguration Research Initiatives6 min
Design flows2 min
5 heures pour terminer

Closing remarks and future directions

We are working at the edge of the research in the area of reconfigurable computing. FPGA technologies are not used only as standalone solutions/platforms but are now included into cloud infrastructures. They are now used both to accelerate infrastructure/backend computations and exposed as-a-Service that can be used by anyone. Within this context we are facing the definition of new research opportunities and technologies improvements and the time cannot be better under this perspective. What it is needed now is new platform creation tools, monitoring and profiling infrastructure, better runtime management systems, static and dynamic workload partitioning, just to name a few possible areas of research. This module is concluding this course but posing interesting questions towards possible future research directions that may also point the students to other Coursera courses on FPGAs.

1 vidéo (Total 5 min), 3 lectures, 1 quiz
3 lectures
Virtualized Execution Runtime for FPGA Accelerators in the Cloud [suggested readings]1h 45min
A cloud-scale acceleration architecture [suggested readings]2 h
Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center [suggested readings]1h 30min
1 exercice pour s'entraîner
Closing remarks and future directions2 min
8 avisChevron Right

Principaux examens pour FPGA computing systems: Background knowledge and introductory materials

par DBMay 10th 2018

Good introduction to reconfigurable computing with FPGAs. Concepts are clearly explained, and examples are illustrative and easy to follow. Lots of papers and additional content to read.

par AEJan 3rd 2019

Perfect course for anyone interested in knowing more about FPGA internals and heterogeneous computing. Thanks for this clear and perfect course and for all the staff efforts.



Marco Domenico Santambrogio

Associate Professor
DEIB - Dept. of Electronics, Information and Bioengineering

À propos de Politecnico di Milano

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