À propos de ce cours : This course is for anyone passionate in learning how a hardware component can be adapted at runtime to better respond to users/environment needs. This adaptation can be provided by the designers, or it can be an embedded characteristic of the system itself. These runtime adaptable systems will be implemented by using FPGA technologies. Within this course we are going to provide a basic understanding on how the FPGAs are working and of the rationale behind the choice of them to implement a desired system. This course aims to teach everyone the basics of FPGA-based reconfigurable computing systems. We cover the basics of how to decide whether or not to use an FPGA and, if this technology will be proven to be the right choice, how to program it. This is an introductory course meant to guide you through the FPGA world to make you more conscious on the reasons why you may be willing to work with them and in trying to provide you the sense of the work you have to do to be able to gain the advantages you are looking for by using these technologies. We rely on some extra readings to provide more information on the topic covered in this course. Please NOTE that most of the time, these documents are provided through the IEEE Xplore Digital Library, which means that, to access them, you have to have a valid IEEE subscriptions, either does by yourself or through your university/company. The course has no prerequisites and avoids all but the simplest mathematics and it presents technical topics by using analogizes to help also a student without a technical background to get at least a basic understanding on how an FPGA works. One of the main objectives of this course is to try to democratize the understanding and the access to FPGAs technologies. FPGAs are a terrific example of a powerful technologies that can be used in different domains. Being able to bring this technologies to domain experts and showing them how they can improve their research because of FPGAs, can be seen as the ultimate objective of this course. Once a student completes this course, they will be ready to take more advanced FPGA courses.
Les destinataires de ce cours : Anyone with moderate computer experience should be able to master the materials in this course. This is an introductory course to FPGA, therefore within this context no specific background knowledge is requested. All the necessary background are provided within this course itself. If not directly presented in the videos, students are pointed to the necessary materials either in the form of readings included in this course or as websites/handbooks that can be easily found/accessed.
Créé par : Politecnico di Milano
Enseigné par : Marco Domenico Santambrogio, Associate Professor
DEIB - Dept. of Electronics, Information and Bioengineering
| Niveau | Débutant |
| Engagement | 4-10 hours/week |
| Langue | English |
| Comment réussir | Réussissez tous les devoirs notés pour terminer le cours. |
| Notes des utilisateurs |
Programme de cours
SEMAINE 1
A Bird's Eye View on Adaptive Computing Systems
Nowadays the complexity of computing systems is skyrocketing. Programmers have to deal with extremely powerful computing systems that take time and considerable skills to be instructed to perform at their best. It is clear that it is not feasible to rely on human intervention to tune a system: conditions change frequently, rapidly, and unpredictably. It would be desirable to have the system automatically adapt to the mutating environment. This module analyzes the stated problem, embraces a radically new approach, and it introduces how software and hardware systems ca ben adjusted during execution. By doing this, we are going to introduce the Field Programmable Gate Arrays (FPGA) technologies and how they can be (re)configured.
7 vidéos, 5 lectures
- Vidéo: Reconfiguration in Everyday Life
- Vidéo: The Needs for Adaptation: an overview
- Reading: Self-Aware Adaptation in FPGA-based Systems [suggested readings]
- Reading: Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores [suggested readings]
- Vidéo: FPGA and reconfiguration: a 1st definition
- Reading: Reconfigurable computing: a survey of systems and software [suggested readings]
- Vidéo: Runtime management
- Reading: ReconOS: An Operating System Approach for Reconfigurable Computing [suggested readings]
- Reading: R3TOS-Based Autonomous Fault-Tolerant Systems [suggested readings]
- Vidéo: Programmable System-on-Chip
- Vidéo: Programmable System-on-Multiple Chip
Noté: Reconfigurations
Noté: History of Reconfiguration
Noté: FPGA and reconfiguration
Noté: Programmable SoC Vs SoMCs
Noté: Runtime management
An introduction to Reconfigurable Computing
Traditionally, computing was classified into General-Purpose Computing performed by a General-Purpose Processor (GPP) and Application-Specific Computing performed by an Application-Specific Integrated Circuit (ASIC). As a trade-off between the two extreme characteristics of GPP and ASIC, reconfigurable computing has combined the advantages of both. On one hand reconfigurable computing can have better performance with respect to a software implementation but paying this in terms of time to implement. On the other hand a reconfigurable device can be used to design a system without requiring the same design time and complexity compared to a full custom solution but being beaten in terms of performance. The main advantage of a reconfigurable system is its high flexibility, while its main disadvantage is the lack of a standard computing model. In this module we are presenting a first definition of reconfigurable computing, describing the rationale behind it and introducing how this field has been influenced by the introduction of the FPGAs.
5 vidéos, 4 lectures
- Vidéo: Reconfigurable Computing: HW vs SW
- Vidéo: On how to improve the Reconfigurable computing performance via CAD improvements
- Vidéo: FPGA-Based Reconfigurable Computing
- Reading: A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization [suggested readings]
- Reading: A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture [suggested readings]
- Vidéo: System design space exploration and rationale behind partial reconfiguration
- Reading: Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs [suggested readings]
- Reading: A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms [suggested readings]
Noté: Reconfigurable Computing Module
Noté: Performance
SEMAINE 2
Reconfigurable Computing and FPGAs
From the mid-1980s, reconfigurable computing has become a popular field due to the FPGA technology progress. An FPGA is a semiconductor device containing programmable logic components and programmable interconnects but no instruction fetch at run time, that is, FPGAs do not have a program counter. In most FPGAs, the logic components can be programmed to duplicate the functionality of basic logic gates or functional Intellectual Properties (IPs). FPGAs also include memory elements composed of simple flip-flops or more complex blocks of memories. Hence, FPGA has made possible the dynamic execution and configuration of both hardware and software on a single chip. This module provides a detailed description of FPGA technologies starting from a general description down to the discussion on the low-level configuration details of these devices, to the bitstream composition and the description of the configuration registers.
8 vidéos, 3 lectures
- Vidéo: FPGA Basic Block: CLBs and IOBs
- Vidéo: FPGA Basic Block: Interconnections
- Vidéo: FPGA Configuration: an overview
- Vidéo: More Details on How To Configure and FPGA: the bitstream files
- Vidéo: Bitstream Composition
- Vidéo: Configuration Registers
- Reading: Note on the "Resources"
- Vidéo: How to handle the complexity of an FPGA-based system
- Reading: Physical design for FPGAs [suggested readings]
- Reading: Multi-Million Gate FPGA Physical Design Challenges [suggested readings]
Noté: Getting familiar with FPGAs
Noté: FPGA configuration and Bitstream
Examples on how to configure an FPGA
FPGA design tools must provide a design environment based on digital design concepts and components (gates, flip-flops, MUXs, etc.). They must hide the complexities of placement, routing and bitstream generation from the user. This module is not going through these steps in details, an entire course will be needed just for this, but it is important at least to have an idea of what it is happening behind the scene to better understand the complexity of the processes carried out by the tools you are going to use. Within this context, this module guides you through a simple example, which is abstracting the complexity of the underlying FPGA, starting from the description of the circuit you may be willing to implement to the bitstream used to configure the FPGA.
6 vidéos
- Vidéo: From the LUT to the CLB configuration example
- Vidéo: A simplified FPGA and its configuration settings
- Vidéo: An Example on how to implement a circuit on a simplified FPGA
- Vidéo: An Example on how to implement a circuit on a simplified FPGA: bitstram generation phase - CLBs
- Vidéo: An Example on how to implement a circuit on a simplified FPGA: bitstram generation phase - SBs and routing
Noté: LUT and CLB
Noté: Physical design
SEMAINE 3
An Introduction to Reconfigurations
Before continuing in this terrific journey in the reconfigurable computing area, it can be useful to define a common language. Obviously, some of these terms have been already used but it is now time to better understand them and to make some order before continuing with more advanced concepts. Furthermore, as we know, FPGA configuration capabilities allow a great flexibility in hardware design and, as a consequence, they make it possible to create a vast number of different reconfigurable systems. These can vary from systems composed of custom boards with FPGAs, often connected to a standard PC or workstation, to standalone systems including reconfigurable logic and General Purpose Processors, to System-on-Chip's, completely implemented within a single FPGA mounted on a board, with only few physical components for I/O interfacing. There are different models of reconfiguration, and a scheme to classify them is presented in this module. We can consider this module as a transitional/turning point module. We have been exposed to some terminology and concepts and we are now ready to move forward. To do this, we need to combine all the pieces of the puzzles together and to invest a bit at looking at the overall picture, and this is exactly what this module has been designed for.
5 vidéos, 2 lectures
- Vidéo: The 5 W's
- Vidéo: Reconfigurable Computing as an Exstension of HW/SW Codesing
- Reading: Design methodology for partial dynamic reconfiguration: a new degree of freedom in the HW/SW codesign [suggested readings]
- Vidéo: A Classification of SoC Reconfigurations
- Vidéo: A Classification of SoMC Reconfigurations
- Reading: Performance of partial reconfiguration in FPGA systems: A survey and a cost model [suggested readings]
Noté: Functionalities and their implementations
Noté: Module Review
Towards Partial Dynamic Reconfiguration and Complex FPGA-based systems
The reconfiguration capabilities of FPGAs give the designers extended flexibility in terms of hardware maintainability. FPGAs can change the hardware functionalities mapped on them by taking the application offline, downloading a new configuration on the FPGA (and possibly new software for the processor, if any) and rebooting the system. Reconfiguration in this case is a process independent of the execution of the application. A different approach is the one that considers reconfiguration of the FPGA as part of the application itself, giving it the capability of adapting the hardware configured on the chip resources according to the needs of a particular situation during the execution time. In this case we are referring to this reconfiguration as dynamic reconfiguration and the reconfiguration process is seen as part of the application execution, and not as a stage prior to it. This module illustrates a particular technique, which is extending the previous two, that has been viable for most recent FPGA devices, Partial Dynamic Reconfiguration. To fully understand what this technique is, the concepts of reconfigurable computing, static and dynamic reconfiguration, and the taxonomy of dynamic reconfiguration itself must be analyzed. In this way partial dynamic reconfiguration can be correctly placed in the set of system development techniques that it is possible to implement on a modern FPGA chip.
8 vidéos, 4 lectures
- Vidéo: How to use FPGA Reconfiguration to face area issues
- Vidéo: How to deal with the Reconfiguration runtime overhead
- Vidéo: Recurring modules to reuse them to reduce the Reconfiguration time
- Vidéo: Partial Reconfiguration to reduce the Reconfiguration runtime overhead
- Vidéo: Runtime management to explore alternative implementations
- Reading: Operating system runtime management of partially dynamically reconfigurable embedded systems [suggested readings]
- Vidéo: Bitstreams relocation
- Reading: Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture [suggested readings]
- Vidéo: Bitstreams relocation and virtual homogeneity
- Reading: A runtime relocation based workflow for self dynamic reconfigurable systems design [suggested readings]
- Reading: Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux [suggested readings]
Noté: Reconfigurable System
Noté: Partial reconfiguration
SEMAINE 4
Design Flows
After presenting different solutions proposed to design and implement dynamic reconfigurable systems, this module will describe a general and complete design methodology that can be followed as a guideline for designing reconfigurable computing systems. To design and implement a reconfigurable computing system, designers need Computer-Aided Design (CAD) tools for system design and implementation, such as a design analysis tool for architecture design, a synthesis tool for hardware construction, a simulator for hardware behavior simulation, and a placement and routing tool for circuit layout. We may build these tools ourselves or we can also use commercial tools and platforms for reconfigurable system design. The first choice implies a considerable investment in terms of both time and effort to build a specific and optimized solution for the given problem, while the second one allows the re-use of knowledge, cores, and software to reach a good solution to the same problem more rapidly. This module is guiding the students through an historical view on how CAD frameworks evolved through the years. This is done to show how fast the technology is evolving and the rationale behind the choice made to improve the users experience when working with an FPGA-based system. Not only commercial tools are described, but also the personal journey done by the course instructor and his research team, starting from his early days as a PhD up to the research challenges they are nowadays working on.
9 vidéos, 7 lectures
- Vidéo: Partial Reconfiguration Design Flows
- Vidéo: Xilinx Difference Based Partial Reconfiguration
- Vidéo: Xilinx Module Based Partial Reconfiguration
- Vidéo: Xilinx Partial Reconfiguration (PR) Flow
- Vidéo: Moudle Based vs Partial Reconfiguration Design Flows
- Reading: Vivado Design Suite Tutorial, Partial Reconfiguration, UG947 (v2016.1) April 6, 2016 [suggested readings - handbook - PDF]
- Reading: Vivado Design Suite User Guide, Partial Reconfiguration, UG909 (v2016.1) April 6, 2016 [suggested readings - handbook - PDF]
- Vidéo: Rationale behind DRESD and the work done by the Politecnico di Milano
- Reading: Dynamic Reconfigurability in Embedded System Design [suggested readings]
- Reading: A design methodology for dynamic reconfiguration: the Caronte architecture [suggested readings]
- Vidéo: From DRESD to CHANGE and ASAP, two new research initiatives from the Politecnico di Milano
- Reading: Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation [suggested readings]
- Vidéo: CAOS: from embedded to heterogeneous distributed FPGA-based computing systems
- Reading: Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project [suggested readings]
- Reading: The Role of CAD Frameworks in Heterogeneous FPGA-Based Cloud Systems [suggested readings]
Noté: Abstractions
Noté: Politecnico di Milano Partial Reconfiguration Research Initiatives
Noté: Design flows
Closing remarks and future directions
We are working at the edge of the research in the area of reconfigurable computing. FPGA technologies are not used only as standalone solutions/platforms but are now included into cloud infrastructures. They are now used both to accelerate infrastructure/backend computations and exposed as-a-Service that can be used by anyone. Within this context we are facing the definition of new research opportunities and technologies improvements and the time cannot be better under this perspective. What it is needed now is new platform creation tools, monitoring and profiling infrastructure, better runtime management systems, static and dynamic workload partitioning, just to name a few possible areas of research. This module is concluding this course but posing interesting questions towards possible future research directions that may also point the students to other Coursera courses on FPGAs.
1 vidéo, 3 lectures
- Reading: Virtualized Execution Runtime for FPGA Accelerators in the Cloud [suggested readings]
- Reading: A cloud-scale acceleration architecture [suggested readings]
- Reading: Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center [suggested readings]
Noté: Closing remarks and future directions
FAQ
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From 2014 Politecnico di Milano started the release of several MOOCs, developed by the service for digital learning METID (Methods and Innovative Technologies for Learning), giving everybody the chance to enhance personal skills.
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Notation et examens
Good introduction to reconfigurable computing with FPGAs. Concepts are clearly explained, and examples are illustrative and easy to follow. Lots of papers and additional content to read.
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Very good course, instructor was very good. Quizes were challenging and pcae of course was good