À propos de ce cours

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Niveau intermédiaire
Approx. 18 heures pour terminer
Anglais
Sous-titres : Anglais

Compétences que vous acquerrez

Primality TestVerilogDigital DesignStatic Timing Analysis
Certificat partageable
Obtenez un Certificat lorsque vous terminez
100 % en ligne
Commencez dès maintenant et apprenez aux horaires qui vous conviennent.
Dates limites flexibles
Réinitialisez les dates limites selon votre disponibilité.
Niveau intermédiaire
Approx. 18 heures pour terminer
Anglais
Sous-titres : Anglais

Offert par

Logo Université du Colorado à Boulder

Université du Colorado à Boulder

Commencez à travailler pour obtenir votre master

Ce cours fait partie du diplôme intégralement en ligne Master of Science in Electrical Engineering de Université du Colorado à Boulder. Si vous êtes admis au programme complet, vos cours seront pris en compte dans votre apprentissage diplômant.

Programme du cours : ce que vous apprendrez dans ce cours

Évaluation du contenuThumbs Up94%(2,629 notes)Info
Semaine
1

Semaine 1

4 heures pour terminer

What's this programmable logic stuff anyway? History and Architecture

4 heures pour terminer
9 vidéos (Total 46 min), 4 lectures, 2 quiz
9 vidéos
Course Overview6 min
1. Welcome to the world of programmable logic and FPGA design1 min
2. A Brief History of Programmable Logic9 min
3. CPLD Architecture5 min
4. LUTs and FPGA Architecture8 min
5. LUTs for Logic Design2 min
6. Designing Adders6 min
7. Designing Multipliers3 min
4 lectures
About This Course10 min
Hardware Requirements10 min
Week 1 Suggested Readings1h 20min
Week 2 Assignment Instructions and Files10 min
1 exercice pour s'entraîner
Mission 002: Week 1 Quiz30 min
Semaine
2

Semaine 2

4 heures pour terminer

FPGA Design Tool Flow; An Example Design

4 heures pour terminer
11 vidéos (Total 121 min), 1 lecture, 3 quiz
11 vidéos
2. Downloading Quartus Prime2 min
3. Installing Quartus Prime2 min
4. Introducing Quartus Prime11 min
5. Create a design project in Quartus Prime7 min
6. Create a design in Quartus Prime13 min
7. Compile a Design17 min
8. View the RTL16 min
9. Timing Analysis with Time Quest I9 min
10. Timing Analysis with Time Quest II16 min
11. Simulate a design with ModelSim17 min
1 lecture
Week 2 Suggested Readings20 min
2 exercices pour s'entraîner
Mission 003 : Practice Opportunity30 min
Mission 005: Week 2 Quiz30 min
Semaine
3

Semaine 3

3 heures pour terminer

FPGA Architectures: SRAM, FLASH, and Anti-fuse

3 heures pour terminer
8 vidéos (Total 80 min), 2 lectures, 1 quiz
8 vidéos
2. Xilinx CPLD Architecture7 min
3. Xilinx Small FPGAs8 min
4. Xilinx Large FPGAs11 min
5. Altera CPLDs and Small FPGAs8 min
6. Altera Large FPGAs9 min
7. Microsemi Single-chip FPGA solutions14 min
8. Lattice Single-Chip FPGA solutions14 min
2 lectures
Week 3 Suggested Readings1h 20min
Week 4 Assignment Instructions and Files10 min
1 exercice pour s'entraîner
Mission 006: Week 3 Quiz30 min
Semaine
4

Semaine 4

6 heures pour terminer

Programmable logic design using schematic entry design tools

6 heures pour terminer
10 vidéos (Total 180 min), 1 lecture, 2 quiz
10 vidéos
2. Advanced Schematic Entry for FPGA Design- Drawing and Hierarchy26 min
3. Improving Productivity with IP Blocks25 min
4. Improving Timing with Pipelining18 min
5. FPGA IO: Getting In and Getting Out8 min
6. Pin Assignments: Making them Spot On!20 min
7. Programming the FPGA10 min
8. Becoming one with Q: Qsys System Design20 min
9.a Becoming one with Q Part II: Qsys System Design Finishing Touches25 min
9.b Becoming one with Q Part III: Qsys System Design Finishing Touches19 min
1 lecture
Week 4 Suggested Readings1h 10min
1 exercice pour s'entraîner
Mission 008: Week 4 Quiz30 min

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