This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Hardware Description Languages for FPGA Design
Université du Colorado à BoulderÀ propos de ce cours
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Certificat partageable
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100 % en ligne
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Dates limites flexibles
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Niveau intermédiaire
Approx. 36 heures pour terminer
Anglais
Sous-titres : Anglais
Compétences que vous acquerrez
Writing Code in VerilogSimulating FPGA DesignsDesigning FPGA LogicDesigning Test BenchesWriting code in VHDL
Certificat partageable
Obtenez un Certificat lorsque vous terminez
100 % en ligne
Commencez dès maintenant et apprenez aux horaires qui vous conviennent.
Dates limites flexibles
Réinitialisez les dates limites selon votre disponibilité.
Niveau intermédiaire
Approx. 36 heures pour terminer
Anglais
Sous-titres : Anglais
Offert par
Université du Colorado à Boulder
CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies.
Commencez à travailler pour obtenir votre master
Ce cours fait partie du diplôme intégralement en ligne Master of Science in Electrical Engineering de Université du Colorado à Boulder.
Si vous êtes admis au programme complet, vos cours seront pris en compte dans votre apprentissage diplômant.
Programme du cours : ce que vous apprendrez dans ce cours
8 heures pour terminer
Basics of VHDL
This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.
8 heures pour terminer
10 vidéos (Total 48 min), 2 lectures, 6 quiz
10 vidéos
Why Learn VHDL?1 min
FPGA Design Flow3 min
Intro to VHDL: Finite State Machine3 min
How to speak VHDL, first phrases6 min
VHDL Assignments, Operators, Types3 min
VHDL Rules and Syntax, Interface Ports3 min
VHDL in ModelSim: Download and Install3 min
VHDL in ModelSim: Adding to your Toolkit6 min
Submitting VHDL Programming Assignments11 min
2 lectures
Misson 2-001: Week 1 Readings2 h
Files for Week 1 Programming Assignments10 min
2 exercices pour s'entraîner
VHDL Find the Code Errors30 min
Module 1 Quiz30 min
12 heures pour terminer
VHDL Logic Design Techniques
In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.
12 heures pour terminer
10 vidéos (Total 52 min), 2 lectures, 6 quiz
10 vidéos
Combinatorial Circuits4 min
Synchronous Logic: Latches and Flip Flops4 min
Synchronous Logic: Counters and Registers6 min
Buses and Tristate Buffers3 min
Modular Designs: Components, Generate and Loops in VHDL3 min
Test Benches in VHDL: Combinatorial8 min
Test Benches in VHDL: Synchronous5 min
Memory in VHDL7 min
Finite State Machines in VHDL8 min
2 lectures
Week 2 Readings2 h
Files for Week 2 Programming Assignments10 min
1 exercice pour s'entraîner
Module 2 Quiz30 min
7 heures pour terminer
Basics of Verilog
This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.
7 heures pour terminer
9 vidéos (Total 92 min), 2 lectures, 6 quiz
9 vidéos
Your First Verilog phrase11 min
Verilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing12 min
Verilog Statements and Operators16 min
Verilog Modules, Port Modes and Data Types10 min
Verilog Structure10 min
Testing with ModelSim5 min
Verilog Evaluation11 min
Submitting Verilog Programming Assignments10 min
2 lectures
Week 3 Readings1h 10min
Files for Week 3 Programming Assignments10 min
2 exercices pour s'entraîner
Verilog Find the Errors20 min
Module 3 Quiz30 min
10 heures pour terminer
Verilog and System Verilog Design Techniques
In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.
10 heures pour terminer
10 vidéos (Total 48 min), 2 lectures, 6 quiz
10 vidéos
Combinatorial Circuits5 min
Synchronous Logic: Latches and Flip Flops3 min
Synchronous Logic: Counters and Registers5 min
Buses and Tristate Buffers3 min
Modular Design in Verilog3 min
Testbenches in Verilog7 min
Testbenches in Verilog II2 min
Memory with Verilog4 min
Verilog Finite State Machines7 min
2 lectures
Week 4 Readings15 min
Files for Week 4 Programming Assignments10 min
1 exercice pour s'entraîner
Module 4 Quiz30 min
Avis
Meilleurs avis pour HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN
par MS15 mai 2020
This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.
par RL1 mai 2020
The Verilog course was very good. However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.
par KK4 juin 2020
This is very good course , but i found some little missing details related to reading materials . But this was really very helpful course for me as fresher .
par HH14 mai 2020
The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.
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