Hardware Description Languages for FPGA Design

Ce cours fait partie de la Spécialisation FPGA Design for Embedded Systems

4.3
étoiles
362 évaluations

Timothy Scherr +1 enseignant de plus

Offert par

Dans le cadre du diplôme Master of Science in Electrical Engineering

Spécialisation FPGA Design for Embedded SystemsUniversité du Colorado à Boulder

À propos de ce cours

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design.   It uses natural learning processes to make learning the languages easy.  Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs.  Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained.  After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.

Certificat partageable

Obtenez un Certificat lorsque vous terminez

100 % en ligne

Commencez dès maintenant et apprenez aux horaires qui vous conviennent.

Cours 2 sur 4 dans le

Spécialisation FPGA Design for Embedded Systems

Dates limites flexibles

Réinitialisez les dates limites selon votre disponibilité.

Niveau intermédiaire

Approx. 36 heures pour terminer

Anglais

Sous-titres : Arabe, Français, Portugais (européen), Italien, Vietnamien, Allemand, Russe, Anglais, Espagnol

Compétences que vous acquerrez

Writing Code in VerilogSimulating FPGA DesignsDesigning FPGA LogicDesigning Test BenchesWriting code in VHDL

Certificat partageable

Obtenez un Certificat lorsque vous terminez

100 % en ligne

Commencez dès maintenant et apprenez aux horaires qui vous conviennent.

Cours 2 sur 4 dans le

Spécialisation FPGA Design for Embedded Systems

Dates limites flexibles

Réinitialisez les dates limites selon votre disponibilité.

Niveau intermédiaire

Approx. 36 heures pour terminer

Anglais

Sous-titres : Arabe, Français, Portugais (européen), Italien, Vietnamien, Allemand, Russe, Anglais, Espagnol

Enseignants

Évaluation de l'enseignant

4.32/5 (132 notes)

Timothy Scherr

Senior Instructor and Professor of Engineering Practice

Electrical, Computer, and Energy Engineering

61,348 étudiants

5 cours

Benjamin Spriggs

Lecturer and Scholar of Engineering Practice

Electrical, Computer, and Energy Engineering

17,780 étudiants

1 cours

Offert par

Université du Colorado à Boulder

CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies.

Commencez à travailler pour obtenir votre master

Ce cours fait partie du diplôme intégralement en ligne Master of Science in Electrical Engineering de Université du Colorado à Boulder. Si vous êtes admis(e) au programme complet, vos cours sont pris en compte dans votre apprentissage diplômant.

Programme du cours : ce que vous apprendrez dans ce cours

Semaine

Semaine 1

8 heures pour terminer

Basics of VHDL

This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.

8 heures pour terminer

10 vidéos (Total 48 min), 3 lectures, 6 quiz

10 vidéos

Introduction to Hardware Description Languages for FPGA Design4 min

Why Learn VHDL?1 min

FPGA Design Flow3 min

Intro to VHDL: Finite State Machine3 min

How to speak VHDL, first phrases6 min

VHDL Assignments, Operators, Types3 min

VHDL Rules and Syntax, Interface Ports3 min

VHDL in ModelSim: Download and Install3 min

VHDL in ModelSim: Adding to your Toolkit6 min

Submitting VHDL Programming Assignments11 min

3 lectures

Hardware Description Languages for FPGA Design Assessment Strategy10 min

Misson 2-001: Week 1 Readings2 h

Files for Week 1 Programming Assignments10 min

2 exercices pour s'entraîner

VHDL Find the Code Errors30 min

Module 1 Quiz30 min

Semaine

Semaine 2

12 heures pour terminer

VHDL Logic Design Techniques

In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.

12 heures pour terminer

10 vidéos (Total 52 min), 2 lectures, 6 quiz

10 vidéos

Learning to speak VHDL (Intro)1 min

Combinatorial Circuits4 min

Synchronous Logic: Latches and Flip Flops4 min

Synchronous Logic: Counters and Registers6 min

Buses and Tristate Buffers3 min

Modular Designs: Components, Generate and Loops in VHDL3 min

Test Benches in VHDL: Combinatorial8 min

Test Benches in VHDL: Synchronous5 min

Memory in VHDL7 min

Finite State Machines in VHDL8 min

2 lectures

Week 2 Readings2 h

Files for Week 2 Programming Assignments10 min

1 exercice pour s'entraîner

Module 2 Quiz30 min

Semaine

Semaine 3

7 heures pour terminer

Basics of Verilog

This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.

7 heures pour terminer

9 vidéos (Total 92 min), 2 lectures, 6 quiz

9 vidéos

Verilog for fun and profit (intro)3 min

Your First Verilog phrase11 min

Verilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing12 min

Verilog Statements and Operators16 min

Verilog Modules, Port Modes and Data Types10 min

Verilog Structure10 min

Testing with ModelSim5 min

Verilog Evaluation11 min

Submitting Verilog Programming Assignments10 min

2 lectures

Week 3 Readings1h 10min

Files for Week 3 Programming Assignments10 min

2 exercices pour s'entraîner

Verilog Find the Errors20 min

Module 3 Quiz30 min

Semaine

Semaine 4

10 heures pour terminer

Verilog and System Verilog Design Techniques

In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.

10 heures pour terminer

10 vidéos (Total 48 min), 2 lectures, 6 quiz

10 vidéos

Learning to speak Verilog (intro)3 min

Combinatorial Circuits5 min

Synchronous Logic: Latches and Flip Flops3 min

Synchronous Logic: Counters and Registers5 min

Buses and Tristate Buffers3 min

Modular Design in Verilog3 min

Testbenches in Verilog7 min

Testbenches in Verilog II2 min

Memory with Verilog4 min

Verilog Finite State Machines7 min

2 lectures

Week 4 Readings15 min

Files for Week 4 Programming Assignments10 min

1 exercice pour s'entraîner

Module 4 Quiz30 min

Avis

4.3

98 avis

5 stars
55.76%
4 stars
30.76%
3 stars
7.14%
2 stars
3.02%
1 star
3.29%

Meilleurs avis pour HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN

par DP15 mai 2020

This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.

par RL1 mai 2020

The Verilog course was very good. However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.

par KK4 juin 2020

This is very good course , but i found some little missing details related to reading materials . But this was really very helpful course for me as fresher .

par KP27 oct. 2020

I think this is a good start in learning how to write VHDL and Verilog. I would like to see a next level course or recommendations for further writing code.

Voir tous les avis

À propos du Spécialisation FPGA Design for Embedded Systems

The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include:

Verilog, VHDL, and RTL design for FPGA and CPLD architectures FPGA development tools flow: specify, synthesize, simulate, compile, program and debug Configurable embedded processors and embedded software Use of soft-core and hard-core processors and OS options FPGA System engineering, software-hardware integration, and testing IP development and incorporating 3rd-party IP The capstone course will give the learner the opportunity to practice and implement the concepts covered by building FPGA systems based on low cost evaluation boards.

Foire Aux Questions

Quand aurai-je accès aux vidéos de cours et aux devoirs ?
L’accès à des vidéos de cours et des devoirs dépend de votre type d’inscription. Si vous suivez un cours en mode auditeur libre, vous pourrez voir la plupart des contenus de cours gratuitement. Pour accéder aux devoirs notés et obtenir un certificat, vous devrez acheter une expérience de certificat, pendant ou après avoir assister au cours en tant qu’auditeur libre. Si vous ne visualisez pas l’option auditeur libre :
Il est possible que le cours ne propose pas d’option auditeur libre. Vous pouvez en revanche accéder à un essai gratuit ou faire une demande d'aide financière.
Le cours propose peut-être « Cours complet, aucun certificat » à la place. Cette option vous permet de voir tous les contenus de cours, de soumettre les évaluations requises et d'obtenir une note finale. Cependant, vous ne pourrez pas acheter une expérience de certificat.
À quoi ai-je droit si je m'abonne à cette Spécialisation ?
Lorsque vous vous inscrivez au cours, vous bénéficiez d'un accès à tous les cours de la Spécialisation, et vous obtenez un Certificat lorsque vous avez réussi. Votre Certificat électronique est alors ajouté à votre page Accomplissements. À partir de cette page, vous pouvez imprimer votre Certificat ou l'ajouter à votre profil LinkedIn. Si vous souhaitez seulement lire et visualiser le contenu du cours, vous pouvez accéder gratuitement au cours en tant qu'auditeur libre.
Is financial aid available?
Oui, Coursera offre une Aide Financière aux étudiants qui n'ont pas les moyens d'acquitter les frais. Demandez-la en cliquant sur le lien Aide Financière sous le bouton S'inscrire situé à gauche. Vous devrez remplir un formulaire de demande et vous serez averti(e) si elle est acceptée. Vous devrez répéter cette procédure pour chaque cours de la Spécialisation, y compris pour le Projet Final. En savoir plus.

D'autres questions ? Visitez le Centre d'Aide pour les Etudiants.

Hardware Description Languages for FPGA Design

À propos de ce cours

Compétences que vous acquerrez