This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Ce cours fait partie de la Spécialisation FPGA Design for Embedded Systems
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Spécialisation FPGA Design for Embedded SystemsUniversité du Colorado à BoulderÀ propos de ce cours
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Cours 2 sur 4 dans le
Niveau intermédiaire
Approx. 36 heures pour terminer
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Sous-titres : Arabe, Français, Portugais (européen), Italien, Vietnamien, Allemand, Russe, Anglais, Espagnol
Compétences que vous acquerrez
- Writing Code in Verilog
- Simulating FPGA Designs
- Designing FPGA Logic
- Designing Test Benches
- Writing code in VHDL
Dates limites flexibles
Réinitialisez les dates limites selon votre disponibilité.
Certificat partageable
Obtenez un Certificat lorsque vous terminez
100 % en ligne
Commencez dès maintenant et apprenez aux horaires qui vous conviennent.
Cours 2 sur 4 dans le
Niveau intermédiaire
Approx. 36 heures pour terminer
Anglais
Sous-titres : Arabe, Français, Portugais (européen), Italien, Vietnamien, Allemand, Russe, Anglais, Espagnol
Offert par
Université du Colorado à Boulder
CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies.
Commencez à travailler pour obtenir votre master
Ce cours fait partie du diplôme intégralement en ligne Master of Science in Electrical Engineering de Université du Colorado à Boulder.
Si vous êtes admis(e) au programme complet, vos cours sont pris en compte dans votre apprentissage diplômant.
Programme de cours : ce que vous apprendrez dans ce cours
8 heures pour terminer
Basics of VHDL
This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.
8 heures pour terminer
10 vidéos (Total 48 min), 3 lectures, 6 quiz
12 heures pour terminer
VHDL Logic Design Techniques
In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.
12 heures pour terminer
10 vidéos (Total 52 min), 2 lectures, 6 quiz
7 heures pour terminer
Basics of Verilog
This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.
7 heures pour terminer
9 vidéos (Total 92 min), 2 lectures, 6 quiz
10 heures pour terminer
Verilog and System Verilog Design Techniques
In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.
10 heures pour terminer
10 vidéos (Total 48 min), 2 lectures, 6 quiz
Avis
Meilleurs avis pour HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN
par MS15 mai 2020
This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.
par RL1 mai 2020
The Verilog course was very good. However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.
par JS6 juin 2021
I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .
par MB23 juin 2021
Good VHDL intro, Verilog was kind of light, especially the reference material. Free Range VHDL was a great reference. The Verilog section needs something similar.
À propos du Spécialisation FPGA Design for Embedded Systems
The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include:
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