What we want to do is the following.

We want to determine the configuration bits for the circuit shown in the figure

to be implemented on our 2 times 2 FPGA device.

Within this context we are assuming that the circuit we have to implement

has been properly described by using an HDL specification, but just to make it more clear

within an online video, we are working with its graphical representation.

Said that, this means that we can consider our graphical representation of the circuit

as the result of the synthesis phase and that we are ready to pass it to the following one...

the Technology Mapping phase.

As we know the technology mapping phase is the phase in charge of finding

the best technology implementation for each of our elements by using a technology library.

In our example, a first solution can be the one shown in the figure.

We have three logic components and we are going to map each of them onto a CLB.

This is definitely a solution, but maybe we can argue that this is not be best one.

We may also want to spend a bit in elaborating what we consider as the best,

but, so far, we can consider this as the number of resources we are using

to implement our specification.

This is not the only way of doing it, but we need something easy and clear to be understood

to drive our process, therefore it can be a reasonable metric.

Now, let us see if we can not do any better...

This second solution is providing us a better outcome of our technology mapping phase.

With the previous solution we were using three CLBs, while now, we are just using 2,

which means 33 percent improvement in terms of resources.

Not bad at all!

Now that we know that we are going to have two CLBs, CLBx and CLBy, to implement

our system, we are interested in knowing which ones of our four CLBs are going to be used.

In the figure we can see that all of the four CLBs are good candidates for being configured

to be CLBx and CLBy.

How to choose?

Well, that is exactly, as we know, what the Placement and Routing phase is here for!

Let’s go first with the placement.

At a very first sight, just to guide you through the entire process,

let’s try to place CLBx onto CLB0.

That means that we are going to configure the top left corner CLB with logic of CLBx.

Now, done this we can move to find a placement for CLBy.

Again, we have three CLBs that are all good candidates.

Let us just pick one, and by doing this we are configuring CLB2,

that was the one on the top right corner, with the logic of CLBy.

Now, I was really keeping it simple, but still this is the Placement and Routing phase,

therefore, we may have found a placement, but what about the routing?

The routing phase is used to connect the elements together.

That means that we have to properly connect the placed CLBs,

but also that we need to interconnect them with the proper I/O blocks,

otherwise data won’t able to flow in and out our system!

Just considering the connections with the inputs blocks.

CLBx is waiting data from inputs zero and two,

while CLBy is looking for data coming from the output of CLBx and input one.

This was something that we were aware of because of the NETLIST we had

and it can bring to a routing using 3 switch boxes as shown in the figure.

Now, the question is, as we did after the first solution during the technology mapping phase,

can we do any better?

Well, in trying of doing it we have to go back to our placement phase

and we have to try a different solution.

We previously mapped CLBx and CLBy onto, respectively, CLB0 and CLB2.

Now, what if we are going to change the placement of CLBy?

What if we are going to place it onto CLB1?

Well, from a pure placement prospective that doesn’t seem to introduce any improvement,

but it doesn’t add an worsening either, therefore it can be an interesting solution

to be explored.

Just a second. Before continuing, I do have to add a note here:

in fact, I don’t want to give you the impression that a worsening solution

does not have to be explored for granted, it does all depend on the algorithm

we are using to drive our placement phase.

A simulated annealing solution will definitely try to explore also some of these situations.

Now, let’s go back to our new solution where CLBy was mapped onto CLB1.

By using this new placement solution we can run our routing algorithm again and…

there we go!

We do have a much way better solution with respect to the previous one!

Before we were using 3 switch boxes, while right now we found a solution that is using just 1!

Well, that’s huge!

We got a 66 percent improvement by just moving CLBy!

That’s great, we are trading up!

But we are not done yet.

We need to connect our elements also to the output pin,

data has to be provided to the external world!

Again, as you can see,

this process is definitely complex, I’m facing it as a sequence of “independent”

sub-problems just to let you get the feeling of the underlying complexity, but in reality,

things are much more complex and this is why we were saying that we need

automatic tools to assist us on this!

Starting from our best solution we can now try to complete our design by connecting CLBy,

which means CLB1, with the output block O7.

In this figure is presenting the solution we have been able to obtain.

As we can see we are using two CLBs to implement our specification

and two Switch Boxes to drive our signals.

Can we stop here?

No, come on...

... this time the answer was easy!

Obviously we are not going to stop here!

We do have to try a different solution!

Again, deciding whether to stop or not is not something that is going on us,

but it is something that we have to pass to our algorithms,

therefore it is necessary to define a stoping criteria to see if it can be worthy to try to find

a better solution or not once that we’ve been able of finding one.

To try a different solution, we have to go back once more to our Placement phase.

We were playing with the CLBy placement, and we are going to do the same now.

We tried to place it on CLB1 and two, let’s see what is happening by placing it on CLB3.

By doing this we have a solution which seems to be very close to the previous one.

We started from a solution based on 2 CLBs and 2 Switch Boxes and we end now

with a solution that is using, again, 2 CLBs and 2 Switch Boxes.

Well... that’s true, but are these two solutions really the same?

To properly answer this question we may want to add the internal configuration

of a Switch Box into the decision process.

We know that each Switch Box is driving three lines, therefore, instead of only considering

the number of Switch Boxes used to implement a solution

we may be interested in knowing the number of lines used to implement a solution.

With this observation in mind, let’s go back to our two solutions

and see if they are really the same!

The last solution we have been able to find was configuring CLBx onto CLB0,

and CLBy onto CLB3 and it was using two Switch Boxes, SB0 and SB3.

By doing this we are configuring one line in SB0 and one line in SB3 to “bring” the CLBx output

to one of the inputs of CLBy.

Furthermore, to connect Input1 to the second output of CLBy we are using a second line in SB3.

Within this context the overall number of lines used to implement the proposed solution is three.

Let’s see what we can obtain from the first implementation we found.

That solution was configuring CLBx onto CLB0, but CLBy was mapped onto CLB1.

From a Switch Boxes point of view, we were using the same set

of the one used in the previous solution, SB0 and SB3.

But, we can appreciate the decision we made in having a different placement for CLBy.

In fact, by having it mapped onto CLB1,

this implies that we are still using one line to connect one input of CLBy

with the output generated by CLBx but we are going to need only one line in SB3

because we just have to connect the output computed by CLBy to the Output block 7.

And this will help us in deciding whether to go with this or with the previous solution...

and I guess we know which one we are going to choose. Right?

An Example on how to implement a circuit on a simplified FPGA

FPGA computing systems: Background knowledge and introductory materials

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