Before this high beams or heterojunction, amorphous silicon, crystalline silicon, let's come back on the performance of crystalline cells as a function of their thickness. So back to crystalline silicon. We here shows a simulation that displays the evolution of the short-circuit current or maximum current density, depending on the thickness of the crystalline silicon cells treated with anti-reflective coating. This simulation shows that to a thickness of the order of 700 microns, is needed to convert the entire solar spectrum by crystalline silicon. But from an economic point of view, it is advantageous to reduce the thickness of silicon. This simulation reveals that reducing the thickness to 300 microns only induces a five percent loss in terms of conversion efficiency. These estimations are calculated without optical optimization of the cell. We can significantly reduce the thickness of the crystalline silicon cell, in order to reduce the cost of PV energy. Thus, the currently commercialized crystalline cells have a thickness of about 200 to 300 microns. We present here the Voc estimation as function of the thickness of the crystalline silicon, whose front face it's texture to improve the optical capping. The Voc increases as the thickness decreases, dotted curve. The decrease of the total semiconductor thickness reduces carrier recombination in the cell. Then, Voc increases with higher densities. However, this increase in Voc at low thicknesses may be limited by surface recombination whose relative effect can be dominant at low thickness, as seen here on the solid curve. Compare the dotted and solid lines. The dotted curve represents the recombination velocity assumed to be equal on both sides, 10 times smaller than the solid line. In this last case, it is found that the Voc particularly does not increase when the thickness decreases, due to surface recombination. Therefore, this simulation reveal that a decrease in the thickness of the cell must be associated with a good surface passivation. The reduction of total thickness of the crystalline silicon, is an economic issue. But what happens experimentally when reducing the thickness of crystalline silicon wafer? Around 100 microns or below with altered by [inaudible] processes. In particular, through diffusion of the dopant to create the p-n junction, often followed by annealing. In this case as seen in this photo, silicon wafers become bended following the high temperature treatment. How to overcome this problem. Passivation of the surface is firstly required in order to reduce the total thickness as we have seen. But the p-n junction is also needed to separate Kias. Hydrogenated amorphous silicon is used to passivate the surface of crystalline silicon, intrinsic amorphous silica in order to reduce defects. Then the growth of adopted amorphous silicon layer allows to create the junction. These two layers are very thin of the order of 10 to 20 nanometers in total, as the transport of the photo generated charges mainly takes place in the crystalline silicon materials. The procedure is the same for the BSF onto the back surface. HIT, Heterojunction with Intrinsic Thin layer is thus obtained, whose preparation method is summarized here. The entire structure is shown here on crystalline silicon in depth. The thin films of amorphous silicon are deposited on both sides of the crystalline silicon diode on BSF. HIT structure is detailed here in application to crystalline silicon. N-doped can be also p-doped, is initially texture in order to ensure the optical capping. Tissue layers can be added especially to improve the optical performances. Let's look at the band diagram of a HIT structures starting with a front. To simplify, we don't mention here as intrinsic layer of amorphous silicon. Let's consider for example; p-doped crystalline silicon. Therefore, the deposited amorphous silicon will be n-doped to cage a junction. At equilibrium, the Fermi level is constant in the system. But the bands on the surface are aligned relative to the vacuum level. There is therefore, a band discontinuity here, Delta Ec. Because the electron affinity of the amorphous silicon and crystalline silicon are different. What are the consequences? One of the advantages of the HIT structure, is we increase the Voc. Since amorphous silicon which is combined with crystalline silicon has a larger band gap, the distance between the two quasi-Fermi levels is increased as compared to the pure crystalline cells. We see that Delta Ev, the distance between the valence band edges, favors the connection of the holes. Since the barrier height is reduced. In contrast, Delta Ec is a barrier for the electrons. But as this barrier is very thin, the electron will be able to cross it by tunnel effect. The band structure of Si:H(p), crystalline silicon and heterojunction is better suited. Consider now the rare contact. Always in the case of crystalline silicon, p-doped; indeed p plus doped amorphous silicon is deposited to create the BSF. Delta Ev creates a barrier for holes. We can be crossed by tunnelling. However, Delta Ec is favorable for BSF since the electrons are repelled by this barrier. At this point, we can make a comparison between the different technologies of the cells based on silicon, crystalline, or amorphous. The optical efficiency of crystalline silicon based cells is excellent. In contrast, thin-film cells are slightly affected by the two tissue layers which create extra interfaces or maybe slightly absorband. Finally, the cells based on crystalline silicon or HIT, exhibit conversion efficiency well above the thin layers. The energy losses by lack of conduction of thermalization of the same order of magnitude as seen in this figure on the right. The recent changes in the best performances of crystalline silicon based cells are presently here. The best cells are produced by Panasonic (HIT) on SunPower. Crystalline silicon with back contact is really turkeys, will just exceed to 25 threshold. The trend is towards very similar efficiencies for the cell and modules as discussed earlier. Thus, it can be predicted that the limit of crystalline silicon technology will be around 26 percent. That is to say, approximately only 10 percent in relative, lower than a theoretical limit. We treated the thin-film cells based on silicon on heterojunction. So transparent conductive oxide layer extensively mentioned, are presented in the next one. Thank you.
