Now let's learn other CMOS logic which is the NAND gate. NAND is NOT-AND that's why it called NAND gate. So NAND gate is the two-input. It can be a three-input, but here, we're learning a two-input, A and the B, output is after it go through the NAND gate comes AB bar. Bar means that not. So truth table of the NAND gate is like this because let's say that AND gate is 1, 1, is only 1. Other than that, everything is zero. Therefore, NOT-AND is opposite to the AND, therefore, 1, 1, 1, 0. If this is the NAND gate, if you want to build the AND gate, then how can you build it using this NAND gate? You put another CMOS inverter to the output of the NAND gate. It inverts the input signal to the output. Therefore, it becomes the AND gate. How to build NAND transistor using the CMOS? This is the circuit of the NAND gate. A is connected to one gate of the NMOS, and the A is also connected to one gate of the PMOS. PMOS is parallely connected, NMOS is serially connected, and one end of the NMOS is grounded. End of the two PMOS is connected to the VDD. B is the same, B connected to the one serially connected NMOS, and B is connected to the one parallely connected PMOS. Now let's learn about the example of the AB equal 1, 1. Let's see there whether the output of the Y becomes zero. One is the high potential. If you applying high potential to the gate, then this transistor is on. Therefore, it is low resistance. B equal to the one, then it transistor one also, very low resistance. So two serially connected NMOS is low resistance, means that they are combination of the two NMOS becomes a very low resistance. What about the PMOS? One high-potential applying to the PMOS as you can learn in CMOS inverter, the transistor is off. If transistor is off, both the PMOS, then these are the high resistance. Two PMOS become the high resistance; therefore, output of Y is pulled down by the NMOS becomes zero. What about the 1, 0? One, transistor on, then low resistance. Zero, transistor off, high resistance. Serial connection of the low resistance and high resistance, these two resistance becomes the high resistance. One transistor on, low resistance. This PMOS is off; therefore, high resistance. Y pulled up by the PMOS, because this is a low resistance, this is a high resistance, pulled up by this PMOS, the output becomes high. What about 0, 0? Zero, 0 transistor off, high resistance, transistor off, high resistance. Transistor on and on; therefore, low resistance. Low resistance pulled up; therefore, one. You can practice by yourself about the NAND gate truth table using CMOS transistor. This is the CMOS NOR gate. NOR gate, as you can tell, not OR. So OR is that 1, 1 is 1; 1, 0 is 1; 0, 1 is 1; 0, 0 is 0. That's the OR, but NOR is opposite to the OR. So this is NOR logic. If you want to build OR gate, then you can put CMOS inverter at the end of the one, then it becomes a OR gate. OR gate, you can express with this, CMOS circle and two input and one output, or NOR gate is A plus B bar. Bar means not. To make a NOR gate using the CMOS, you connecting the circuit like this, two serial connection of the PMOS and two parallel connection of the NMOS using input A, B. Now let's see whether 1, 1 becomes zero in output Y. One high potential to the A, becomes transistor of PMOS, one high, off. Therefore, two serial connection of a high resistance. One, on, on. So low resistance, low resistance. Therefore, Y is pulled down by the NMOS becomes zero. Exactly the same thing with the NAND gate. I want you to practice by yourself. Let's do one more. Zero, 0 becomes a zero transistor on for the PMOS, low resistance, low resistance, high resistance, high resistance. Y is pulled up by the PMOS; therefore, one. This slide shows how you can build CMOS inverter layout. This is the NMOS, n plus, n plus, and p-type substrate. Then this is the gate, and this is the PMOS, p pull and p pull made on n-well. N-well means that the substrate area in here is the n-type silicon. So this is the PMOS. If you look at it in top view, these cross-section is the cut line by like this. So this is the cut line here, this is the top view. Ground electrode and gate electrode connected together for the NMOS and PMOS. One end up the PMOS, one end of to NMOS is connected to each other, that's the Y. One end of the PMOS is connected to the VDD is like this. Then you might ask, why there is p pull and n pull in here? So these p pull unlike the n pull, this n pull becomes a p-n junction, p-n junction. These are the n-p junction, n-p junction. But this p pull is p pull connection. What it does in this p pull is that, the ground potential come to the p pull, and then enclosing this p-type silicon becomes the ground. This n pull is n input contact. This is not p-n junction. VDD potential is influencing n pull, so this n pull is VDD, then this VDD becomes a n-well potential. So n-well potential is the VDD. This is [inaudible] in here. This p pull makes the N-Channel MOSFET. The substrate becomes the ground. You apply the V_in is V_in voltage in reference to the ground, or source, or p-type silicon. So potential of a V_in is the potential reference to p-type silicon V_in. What about the PMOS? You apply gate voltage, V_in reference of the VDD. So if you apply zero volt and VDD is two volt, then this is the minus two volts. So those minus two volt is also reference to the substrate of n-well, n-type silicon, because n-well is the two volt in a VDD
