Welcome to FPGA design for embedded systems. In this video, you will learn how to start and run a timing simulation in ModelSim from Quartus Prime. How to use simulation to verify the correct timing of a VHDL serial adder, and how to interact with the simulation by zooming into signal wave forms to discover timing details. Just a reminder here of the design flow. We are doing the bottom half in this video, after analysis of functional simulation is done, which only determines if the logic is correct and does not include any timing models. After fitting our place and route, the timing simulation can be done which will identify timing violations. These will show up in red on the ModelSim waveform viewer, this simulation can help achieve timing closure. This process is often iterative as shown in the diagram where errors are corrected, you recompile, you re-simulate et cetera until no errors remain. To learn about the FPGA flow, we've worked through a complete example using Quartus Prime and the Altera version of ModelSim. We've already done the functional simulation of this serial adder that you see here which is a good example to work through because it's got synchronous design, and it's got combinational design in it. It is a process that's really well known, you know what you expect the outputs to be and so on so that it can be easily verified. It's just going to take two eight-bit numbers A and B, add them together over a period of time, bit by bit until the result ends up in the sum output. The code for this example is provided in the included using ModelSim.zip file which you can download from the Coursera site. Come simulate with us. You should have Quartus Prime installed. Start Quartus Prime and select New Project, and browse to your new project directory and select serial.qpf in the timing directory now. You might see a message about the use of Cyclone II family in this design. The original timing project might have been done in Cyclone II, you can select Cyclone IV E instead. You could also select Max 10 or other devices. Not all devices have tiny moles associated with them though, but we would encourage you to explore using other devices with this project at a later time just to see what works and what doesn't. But certainly, if you use Cyclone IV E, that's going to work. In Quartus then, open the project serial.qpf in the timing directory. Use Assignments, and then Settings, and then the EDA tools, and then Simulation to set up the simulation. You want to make sure that it looks just like what you see here where the EDA tool that's chosen for simulation is ModelSim Altera, and that it's going to use verilog.hdl, and its interesting that's going to use Verilog for simulation even though the code itself is in VHDL. This works just fine as it turns out. Then you also want to make sure that the settings here are as shown without a test bench and so on. In the design flow, you want to run a full compilation, and of course this is going to take a little bit of time. But once that finishes, you should see everything in green with all the green check box. Then you can also look and see within the project directory on your computer all the files that been created, and you might note the creation of the.vo and the.sdo files, and their setup for three different timing corner cases. Where you have slow processes versus fast processes, anywhere you have very cold temperatures versus very hot temperatures so zero and 85. The worst-case typically, the slowest process with the high temperature, 85 degrees, is going to give you usually the most problems so that'll be the worst-case. That would be the one that we're going to investigate first when we do the timing simulation, but you can do the other corner cases as well just to be sure that you don't have any issues. You start the simulation from Quartus by selecting Tools, and then Run Simulation, and then Gate Level Simulation. You don't want to do an RTL simulation here, you want it to be gate-level, that means that the timing information is in the models. You do this from the top menu, and when you do that, you'll get another dialog box here where it allows you to choose which timing model you want to use, again, we want to choose the slow at 85 degrees. Then ModelSim should start, so you start it from Quartus Prime, had to start it on its own. Because you started it from Quartus Prime now all the Altera models show up in the libraries, which is really helpful in this case, because these have timing information in them. There should be some transcript messages which will indicate that the top level is the serial file that we want to simulate. If you click on ''Simulate'', ''Start simulation'' from the top menu in the library tab that appears, you'll have a start simulation dialog box that'll appear, it'll have a library tab. You want to add the Cyclone IV E and the Altera libraries by browsing to the intelFPGA lite 16.1 ModelSim directory, this is the installation directory for the Quartus tool. It includes all of these libraries within the ModelSim directory. So that's where you would find these and then you would browse and then add those particular libraries in at this point. You need to do that in order for the timing models to be included. Then you want to select serial.vhd, that file from the work library like you normally would, with a resolution set to picoseconds, not nanoseconds as it shows, but picoseconds and hit "Okay" to start simulating. Simulation should begin. The sim window is going to appear as it did before when we were doing functional simulation, and many more signals are going to appear in the object window. You have a lot more signals now in the timing model than you do in the functional model. There's just a lot more nodes to keep track of. The models are more complex, and so you'll see that in the sim window and in the object window. The transcript is also going to show the loading of all the library timing models so that you can see that that work is being done. You can add signals, the waveform window by selecting and dragging the first six. So you click on the top one, hit "Shift" and click on the sixth one and then you're going to get those six and just drag them over to the wave window. Then you also want to scroll down to the bottom to get the reg under sum, reg under A, reg under B, those signals as well. So these are registered versions of all these signals, which we want to look at that are part of the design. Once you do that, then the wave window is going to look something like this. You want to set the simulation time to 20 nanoseconds in the box here. We don't have any test bench still, so you manually, you can add the clock in the reset stimulus just like you did in the functional simulation. Your going to right click on the clock and the waveform window and select "Clock" and put in a period of 20 nanoseconds. You want to make sure to include the units. If you don't, then you're going to end up with a simulation clock period of 20 picoseconds, which this device is not going to handle very well. We want to set that clock period to 20 nanoseconds. Then right-click on the resetn and force it to zero and do the same thing for Start, just like we did before. Now we're ready to hit the down arrow here and simulate for 20 nanoseconds. So we'll run the simulation. Some signals again, are going to be unknown and they'll be shown in red in the transcript window, but then eventually they become driven and you see the values appear at that point then. To continue, now we're ready to set the inputs, so we're going to force A to 157 and B to 43 as before. Make sure that you put the 10 pound in front of the numbers so that it gets interpreted as a decimal number and not a hexadecimal number or a binary number. Once you've done that, then you can right click on these signals and change the radix to unsigned, as we've done before, and set the sum to unsigned as well as depicted in the picture here. Then you want to force resetn and start to one so that the serial addition will start up. We'll run for another 20 nanoseconds only here. Now you can use the cursors to measure the time delay from the clock edge to the A and B register data as it changes. So there's a delay of about 2.3 nanoseconds that we've measured here. So using the cursors to measure that delay. This is a combination of the clocked out delay of the flip-flops in the register and also path delays from the A and B register inputs to the input to the register itself, and also path delays of the clock are all included in all of that. We're going to change the run time then to 200 nanoseconds and run again. So this will get you to the end of the serial addition process. Now you can use the cursors to measure the time delay from the first appearance of the input data until the sum, about 196 nanoseconds. So nine clock cycles will be 180 nanoseconds plus part of one more clock cycles, how much delay it takes in order to do this addition. Then you can also zoom in on the final sum transition, and what you will see, even though it looks like it's just a change from 400-200, it actually happens over a span of time, and the data goes through several values before settling to 200 over about eight-tenths of a nanoseconds, so 800 picoseconds it takes for this to occur. The data bits within this one do not all change at the same time. This is something that you can see happening when you have timing models in a simulation. If you try to look at this particular output, the sum output, in the middle of this transition, you're going to get incorrect data then. So it has to wait until that transition occurs before you look at that value in order for your addition to be correct. So timing matters and the timing simulation helps you see that. In this video, you have learned how to start and run a timing simulation in ModelSim from Quartus Prime, how to use simulation to verify the correct timing of a VHDL serial adder, and how to interact with the simulation by zooming into signal waveforms to discover timing details.
