Welcome again, to FPGA design for embedded systems. Altera has its own version of ModelSim that comes packaged with Quartus prime. It's free, which is great. It's a little more up-to-date than the student edition which you can also use. There's some other advantages for using Altera's version of ModelSim. In the next couple of videos, learn how to make better use of Altera ModelSim. In this video, you will learn how to start and run a functional simulation of ModelSim from Quartus Prime. How to use simulation to verify the correct functional operation of a VHDL serial adder, the example that we'll use. How to interact with the simulation by viewing source code, changing the radix display of signals, and manually forcing signals to values to provide test stimulus. In FPGA development, simulations for design verification are done at two separate times in the design flow. First after analysis, a functional simulation is done, which only determines if the logic is correct, which that can be important of course. But it doesn't include any timing models. After fitting or place and route, a timing simulation can be done which will identify timing violations. These will show up in red on the ModelSim waveform viewer. In VHDL, the signals will acquire the state x as opposed to zero or one and so you can see these clearly. The simulation then can help achieve timing closure. This process is often iterative as shown in the diagram, where errors are corrected, then you recompile, you restimulate, and you do this iteratively until no errors remain. To learn about the FPGA flow, we will work through a complete example using Quartus Prime and the Altera version of ModelSim. Launching ModelSim from Quartus has the advantage of including all the Altera model libraries automatically. You don't have to add them in manually, like you might have to do otherwise. The example is based on a serial adder circuit, as shown in the diagram. We will be using VHDL for this example, but you could do it in Verilog as well. The code for this example is provided in the included used ModelSim.zip file which you can download. Come simulate with us. You should have Quartus Prime installed. Prepare for this exercise by unzipping the using modelsim.zip to a new project directory like C: Altera projects Sim 2 or something else of your choosing. Start Quartus Prime and select New project and browse to your new project directory, and select serial.qpf in the functional directory as the project file. To start the simulation, in the design flow, first you have to run analysis and synthesis, so the code is compiled and that information of those models can pass over to the ModelSim simulator. Then you start the simulation from Quartus by selecting tools and then RTL simulation from the top menu. ModelSim should start then, even though the HDL has been compiled in Quartus, ModelSim can also compile these files. To simulate on the file that is the top level of interest, you select serial.vhd from the work library and then right-click it and select Simulate to start the simulation. Simulation should begin. The sim window appears and signals from the top level appear in the object window, double-clicking on the entities in the sim window will open the source code for that entity. This is one way to make the source code appear then in that right window so that you can examine it, use it to set breakpoints and other things that you might want to do with the source code during simulation. You can add signals to the waveform window by right-clicking on a signal on the object window and then select Add to and then Wave and then Signals in Region. Then you will just get the top level signals for this particular design into the wave window. You can look at signals that are other than the top level there, buried in the hierarchy and some other functions and so on. The signal names start to get to be long, and so sometimes it's difficult to determine what it is you're looking at. But usually at the beginning you just want to look at the top level signals, make sure everything is working right at that level before you start to investigate some of the other components that have been instantiated in the design. We have no testbench in this particular example, so we can still do simulation though by manually adding the clock and reset stimulus. If you right-click on the clock in the waveform window and select clock with period 100, then that will give us a clock with a period of 100 or whatever the time units are in this particular case. You can right click on resetn and force it to a zero. You'll want to do the same thing for the start signal so that everything starts out in a known state. Then if you click on the Run button to the right of the 100 picosecond menu icon, that will run the simulation. Some signals are going to be unknown and they'll be shown in red. Also you'll see them in the transcript window indicating that that's something that you might want to pay attention to. But in this case, they're just simply undriven at this time. You can add some other stimulus. This adder adds A and B together to make a sum. A and B are both eight bits. You can force A to the value of 157 and B to 43 using the same mechanism as we used before. If you right-click on the signals and change the radix to unsigned, it will make it easier to understand what the values are. You can also set the sum to unsigned as well using the process that's depicted here. You can also force resetn and start to be a one, so that allows then the addition process to start. There's a little state machine inside of this that will run the addition of one bit at a time. You can set that simulation time in a text field to 1,000 picoseconds and hit the Run button. We're doing this because it takes about nine clock cycles for this serial adder to complete the addition of 2 eight-bit numbers. If you right-click in the waveform and select Zoom full and put the cursor after the last clock edge, then you can see that the sum is in fact 200. But you'd expect 147 plus 43 is going to be 200. That verifies this circuit works. It is an adder and it adds those two numbers at least correctly. We now have completed the functional simulation of the circuit. You might have some thoughts about the veracity of the results. The timescale in our waveform window is in picoseconds. This does not mean that the circuit will run with a gigahertz clock in your Altera device. The functional simulations time is just an index, so there's no timing models underneath things. The devices are modeled logically only and without any timing information. Picoseconds, nanoseconds, it could be anything. It doesn't really matter in this case. But when you do a timing simulation, then the resolution and the timescale do matter. To get information about timing, timing models have to be inserted and used in the simulation. This requires a different simulation setup. To determine the timing of path delays, a place and route has to be done first before the timing simulation can occur. We'll look at that in the next video. In this video, you have learned how to start and run a functional simulation in ModelSim from Quartus Prime. How to use simulation to verify the correct functional operation of VHDL serial adder, and how to interact with the simulation by viewing source code, changing the radix display of signals, and manually forcing signals to values to provide test stimulus.
