[MUSIC] In this lesson, the second sequential block, the register bank will be implemented. This is it's functional specification in which X is a vector whose components X(0), X(1) and so on, up to 15, are internally stored. Thus this is a sequential block. The behavior of this block depends on the instruction under execution. So, we define the control signal write_reg equal to 1 if the executed instruction implies the updating of one of the components of X, that is to say, if the instruction is ASSIGN VALUE, DATA INPUT or an OPERATION, and is equal to 0 in all other cases. Then, with the definition of this control signal WRITE_REG, the functional specification is slightly modified. The inputs of the register bank are the control signal WRITE_REG, and 3 indexes K, I and J included in the instruction. There is also a REG_IN input that comes from the INPUT SELECTION block. There are two outputs LEFT_OUT and RIGHT_OUT, and the functional specification can be simplified. Actually, when a new data is written within the register bank, it comes from the INPUT SELECTION block, that is to say, from the REG_IN input of this block, and is written within memory element X(k) defined by the first index. So, if write_reg is equal to 1, then X(k) is updated with the value of REG_IN. And as regards the outputs, there are selected by indexes I and J. So LEFT_OUT is equal to X(i) and RIGHT_OUT is equal to X(j). Here is a straightforward implementation using a decoder that selects the memory element X(k) that will be updated, a set of AND gates that make active or non-active the decoder outputs, 16 registers controlled by signals EN0, EN1, and so on, and two 16-data-input multiplexers that select the memory elements X(i) and X(j) that are transmitted to the outputs LEFT_OUT and RIGHT_OUT. This circuit can be described in VHDL. After making visible several IEEE packages as well as our user defined package, the entity is declared. It gives the list of inputs and outputs: REG_IN is an M-bit input vector; WRITE_REG is a control signal (a bit); i, j and k are indexes; they are 4-bit vectors; LEFT_OUT and RIGHT_OUT are two output vectors (M-bit vectors) and clk, as before, is a non-represented in the circuit clock signal that synchronizes, that will synchronize the operations of the 16 registers. Within the architecture a user-defined type MEMORY is defined. It is an array of 16 elements, each of them being an M-bit vector. Then a signal X is declared: it is the set of memory elements X(0), X(1), X(2) and so on. A signal EN (enable) is also declared. It is the set of 16 enable signals that control the 16 registers. Then four processes describe the circuit. The first process describes the address decoder and the set of AND gates. For that a CONVERT_TO_INTEGER function, included in the arithmetic package, has been used. The process body is a loop. For every index I of the loop, if I coincides with index K (index K converted to an integer) then EN(I) will be equal to WRITE_REG. If I is smaller than K or greater than K, then EN(i) is equal to 0. In other words, EN(i) is equal to 1 if the output number I of the decoder is equal to 1, and, at the same time, WRITE_REG is equal to 1. A second process describes the set of registers. This process is the only one sensitive to a nonrepresented clock signal, CLK. Then, on a positive edge of CLK, when EN(0) is equal to 1 then X(0) will be updated with the REG_IN input; when EN(1) is equal to 1 then X(1) is updated with the REG_IN input, and so on. The third process describes the first (leftmost) multiplexer. If I is equal to 000, that is to say if it represent number 0, then the output LEFT_OUT is equal to X(0); if I represent (for example) number 14 then LEFT_OUT is equal to X(14), and so on. And the fourth process describes the other multiplexer. The difference is that now we use index J instead of index I. Summary. The sequential block REGISTER BANK has been implemented, and a VHDL model has been generated.