[MUSIC] This lesson and the two following deal with the implementation of the sequential blocks, namely the "output selection" block, the "register bank" and the "go to" block. The first sequential block that we will implement is the "output selection". This is its functional specification. We have already commented before that OUT0, OUT1, and so on, are registered outputs. That means that if the value of an output port, say OUTi, is not updated by a DATA_OUTPUT instruction or by an OUTPUT_VALUE instruction, then OUTi keeps the same value as before. So, this is a sequential circuit. The behavior of this block depends on the instruction under execution. So, we define two control signals: "out_en" for output enable and "out_sel" for output selection. out_en is equal to 1 if the executed instruction is DATA_OUTPUT or OUTPUT_VALUE, and is equal to 0 in the other cases. And "out_sel" is equal to 1 if the executed instruction is a DATA_OUTPUT, and to 0 if the executed instruction is OUTPUT_VALUE. Its value is left undefined in the other cases. Then, with the definition of the control signals, the functional specification is modified. The inputs of the "output selection" block are two control signals, out_en and out_sel; i, an index included within the instruction. A, a number included in the instruction, and "reg", a value that comes from the register bank. And the outputs are the eight output ports. Thus the modified model or specification is this one: when out_en and out_sel are equal to 11, then the output number i is connected to the "reg" input. When 10, the output number i is connected to A, and in the other cases no operation is performed. That means that the value of the output ports is unchanged. Here is a straightforward implementation using an address decoder that selects the output port that will be updated; a set of AND gates that make active or non active the address decoder outputs. Then eight registers controlled by the signals EN0, EN1, and so on. And a 2-data-input multiplexer that selects the data to be stored within the selected output register: can be either A or a value that comes from the register bank. This circuit can be described in VHDL. After making visible the IEEE package and also our user-defined package, the entity is declared. It gives the list of inputs and outputs. Namely, inputs A and reg that are vectors; control signals out_enable and out_sel that are bits, and index i, a 3-bit vector that selects one of the eight output ports; and there are eight outputs, the eight output ports that are vectors. There is also a clock signal, not represented in this circuit, but necessary to synchronize the working of the output registers. Within the architecture, signal EN, that is the set of enable signals, signal DEC_OUT, that is the set of decoder outputs, and signal to_ports, the output of the multiplexer, are declared. Then four processes describe the circuit. The first process describes the address decoder: if index i is equal to 000 (represents number 0) then component 0 of DEC_OUT is equal to 1; if index i represent number 1, then component number 1 is equal to 1, and so on. If i represent number 6, then component number 6 is equal to 1, and in the last case, component number 7 is equal to 1. The second process describes the set of AND gates. It's a loop. For every index i. the value of ENABLE(i), component number i of vector ENABLE, is equal to the AND function (the Boolean AND function) of component number i of DEC_OUT and of input control signal out_en. The third process describes this multiplexer. If control signal out_sel is equal to 0, then to_ports is connected to input A, and if it's equal to 1, then to_ports is connected to input "reg". The fourth process, describes the output registers. In this process, the only one sensitive to a non-represented clock signal clk, the condition "if clk'event and clk = '1'" is used. It is the way a positive edge of clk is represented in VHDL and, by the way, this condition confirms that this is a sequential circuit. Then, on a positive edge of clk, when component 0 of EN is equal to 1 (this component), then output 0 is updated with the value of to_ports. If EN(1), component 1 of EN, is equal to 1, the OUT1 is updated with the to_ports value, and so on. In all other cases, in particular when out_en = 0, and thus all components of vector EN are equal to 0, there is no operation, that means that the value of the output ports remains unchanged. Summary. The sequential output selection block has been implemented and the VHDL model has been generated.