[MUSIC] Today, we start the second part of the design of our processor. The first part was the processor specification. First, we gave a functional specification, and then a structural specification under the form of a diagram consisting of five blocks. All five blocks have been specified by the function or algorithm that they execute. Now, in this second part of our design, every block must be implemented with digital components such as logic gates, multiplexers, flip flops and so on. And, furthermore, to each block, we will associate a VHDL model. The first block that we will implement is the input selection. This is its functional specification. Observe that it is a combinational block as the value of its output to_reg only depends on the current value of its inputs: "instruction", the eight input ports and "result". The behavior of this block depends on the instruction under execution. So, we define two control signals equal to 00 if the executed instruction is ASSIGN_VALUE, equal to 01 if the instruction is DATA_INPUT, to 10 if the executed instruction is OPERATION, and whose values are left undefined in the other cases. Then, with the definition of those control signals, the functional specification is modified. Now the inputs of the input selection block are j, an index included within the instruction that defines which input port is selected, A, a number also included within the instruction, the control signals defined by the table, the input ports, and the result of an operation. This is the modified specification. When the control signals are equal to 00, to_reg is equal to A, when equal to 01, to_reg is equal INj, that is to say, one of the input ports, the input ports selected by index j, when 10, to_reg is equal to the result of an operation, and when equal to 11, the value of to_reg doesn't matter. This is a straightforward implementation using multiplexers. With the 4-data-input multiplexer controlled by the input_control signals, the output to_reg is connected to either A, when the control signals are equal to 00, or to one of the input ports when the control signals are equal to 01, or to "result" when the control signals are equal to 10, and, for instance, to 0, when the control signals are equal to 11. The input port selection is implemented by another multiplexer with eight data inputs. This circuit can be described in VHDL. We have defined a package that includes the declaration of a constant m equal to 8. We do that in order to make our description a bit more general. Our processor stores and processes 8-bit data; nevertheless, by only changing the definition of constant m within the package. changing it to (for example) m = 16, we would get the description f a 16-bit processor. Another option would be the use of generic parameters within the entity definitions and the entity instantiations. After making visible the IEEE package, as well as our user-defined package, the entity is declared. This declaration gives the list of all inputs and outputs, namely, the eight input ports that are m-bit vectors; A and "result" are also m-bit vectors; j, the index that selects one of the input ports, is a 3-bit vector, the input signal "input_control" is a 2-bit vector, and to_reg, the output, is an m-bit vector. Within the architecture, signal selected_port is declared. It is the output of the first multiplexer. And then each multiplexer is described by a process. The first multiplexer, this one, is described by this process. In the case that j, the index j, is 000, then the selected_port (here) is equal to IN0; when 001, it's equal to IN1 and so on. The second multiplexer, this one, is described by another process. When input_control is 00, then to_reg is connected to A; when equal to 01, it is connected to selected_port (it was this signal); when 10, to result, and when another value, it is connected to, for example, constant value 0. The second combinational block is the computation resource. Its functional definition is very simple. If the control input, f, is equal to 0, then the output result is the sum left_in + right_in, and if this control input, f, included within the instruction, if it's equal to 1, then the output result is the difference between left_in and right_in. The corresponding circuit is an adder/subtractor, and it can be implemented sing the methods and components described in lesson 1 of week 4. It can also be described by this VHDL model using the arithmetic IEEE packages. This is the entity declaration. The list of inputs and output is: left_in and right_in are m-bit vectors; f, the control input, is a bit, and the result is also an m-bit vector. And when using the arithmetic packages, the architecture is very simple and amounts to this "if then else" construct: if f = 0, then the result is left_in + right_in, and if f = 1, the result is the difference left_in - right_in. In fact, the synthesis tool that will translate this VHDL description to a circuit knows the definitions included within the IEEE arithmetic packages, and will instantiate an adder/subtractor. Summary of this lesson: the two combinational blocks, that is to say, input selection and computation resource, have been implemented, and VHDL models have been generated.