2-Level Logic: The Reduce-Expand-Irredundant Optimization Loop

Loading...
En provenance du cours de Université de l'Illinois à Urbana-Champaign
VLSI CAD Part I: Logic
52 notes
Université de l'Illinois à Urbana-Champaign
52 notes
À partir de la leçon
2-Level Logic Synthesis, and Multi-Level Logic Synthesis via the Algebraic Model
In Week 3, we will move from "representing" things to "synthesizing" things. In this case, synthesis means "optimization", or maybe the word "minimization" is more familiar from hand work with Kmaps or Boolean algebra.

Rencontrer les enseignants

  • Rob A. Rutenbar
    Rob A. Rutenbar
    Adjunct Professor
    Department of Computer Science

Explorer notre catalogue

Rejoignez-nous gratuitement et obtenez des recommendations, des mises à jour et des offres personnalisées.